High-Speed Source-Synchronous Differential I/O Interfaces in Cyclone 10 GX Devices

background:

My end goal is to implement source synchronous differential IO interface with Cyclone 10 GX devices : 4 data lanes with 1 clock line at 2.5 Gbps with 1.25 GHz.

Cylone 10 GX devices has dedicated LVDS lines with HARD IP Serializer and Deserializer which allow LVDS at 1.434 Gbps. This is a limitation in my application. I am trying to use transceivers for 2.5 Gbps instead of LVDS IO resources.

question:

I am looking for a document or a design example or a reference design for High-Speed Source-Synchronous Differential I/O Interfaces in Cylone 10 GX Devices.

extra information:

For other current GX devices, it is also fine.

I found the following document published at 2006. I am looking for a updated version of it.

https://www.altera.com/en_us/pdfs/literature/hb/sgx/sgx_sgx52013.pdf