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Honored Contributor

7 years ago

High-Speed Source-Synchronous Differential I/O Interfaces in Cyclone 10 GX Devices

background: My end goal is to implement source synchronous differential IO interface with Cyclone 10 GX devices : 4 data lanes with 1 clock line at 2.5 Gbps with 1.25 GHz. Cylone 10 GX devices...

Altera_Forum

Honored Contributor

7 years ago

Hi,

Refer session 5.2 of the handbook.

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Forum Discussion

High-Speed Source-Synchronous Differential I/O Interfaces in Cyclone 10 GX Devices

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