Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHigh-Speed Source-Synchronous Differential I/O Interfaces in Cyclone 10 GX Devices
background: My end goal is to implement source synchronous differential IO interface with Cyclone 10 GX devices : 4 data lanes with 1 clock line at 2.5 Gbps with 1.25 GHz. Cylone 10 GX devices...
Altera_ForumHonored Contributor
Honored ContributorHi,
You can find reference designs for Cyclone10 GX here: https://cloud.altera.com/devstore/platform/?acds_version=any&family=cyclone-10-gx&board=102 You can find the Cyclone10 GX transceiver guide here: https://www.altera.com/documentation/hki1486507600636.html https://www.altera.com/products/fpga/cyclone-series/cyclone-10/cyclone-10-gx/support.html statix10 lvds guide : [url]https://www.altera.com/documentation/sam1439794388346.html (https://www.altera.com/products/fpga/cyclone-series/cyclone-10/cyclone-10-gx/support.html) http://www.alterawiki.com/wiki/high_speed_transceiver_demo_designs_for_current_and_older_families http://www.alterawiki.com/wiki/source_synchronous_interfaces_between_altera_fpgas [/URL]
