hierarchical object access in verilog

Question

Hi,

I have hierarchical object access in my RTL.

During Synthesis i am getting the below error as shown below;

Error (10207): Verilog HDL error at cust_xmr.v(20): can't resolve reference to object "in1"

Error (12152): Can't elaborate user hierarchy "sub3:sub3"

Please let me know if hierarchical access is supported in Quartus for Verilog/Systemverilog designs.

This is urgent and let me know.

Regards,

Freak

altera_forum · Answer

i don't think hierarchical names are supported in Quartus

altera_forum · Answer

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I have hierarchical object access in my RTL.

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This is a language feature intended for use in simulation.

For synthesis, you'll need to use ports on the modules.

Cheers,

Dave

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