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Honored Contributor
Honored Contributorhierarchical object access in verilog
Hi, I have hierarchical object access in my RTL. During Synthesis i am getting the below error as shown below; Error (10207): Verilog HDL error at cust_xmr.v(20): can't resolve reference...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I have hierarchical object access in my RTL. --- Quote End --- This is a language feature intended for use in simulation. For synthesis, you'll need to use ports on the modules. Cheers, Dave
