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Altera_Forum
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13 years ago

hierarchical object access in verilog

Hi, I have hierarchical object access in my RTL. During Synthesis i am getting the below error as shown below; Error (10207): Verilog HDL error at cust_xmr.v(20): can't resolve reference...
Altera_Forum's avatar
Altera_Forum
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13 years ago

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I have hierarchical object access in my RTL.

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This is a language feature intended for use in simulation.

For synthesis, you'll need to use ports on the modules.

Cheers,

Dave