hi someone has offered this question before,and is there any answer for it?

Hi. I have the difficulty to understand the different of set_multicyle_path in system approach and skew approach(FPGA centric) in AN433 doc.

http://www.altera.com/literature/an/an433.pdf

the constraint for system centric approach(pg14),

set_multicycle_path -setup -end 0 -rise_from [get_clocks

data_clock] -rise_to [get_clocks output_clock]

set_multicycle_path -setup -end 0 -fall_from [get_clocks

data_clock] -fall_to [get_clocks output_clock]

the constraint for FPGA centric approach(pg26),

set_multicycle_path -setup -end 0 -rise_from [get_clocks

data_clock] -rise_to [get_clocks output_clock]

set_multicycle_path -setup -end 0 -fall_from [get_clocks

data_clock] -fall_to [get_clocks output_clock]

set_multicycle_path -hold -end -1 -rise_from [get_clocks

data_clock] -rise_to [get_clocks output_clock]

set_multicycle_path -hold -end -1 -fall_from [get_clocks

data_clock] -fall_to [get_clocks output_clock]

Questions:

Why does the FPGA centric approach have extra 2 set_multicyle_path -hold compare to system approach?

I update some as following:

since the two way have different set_false_path later in AN433,

-hold rise->fall,fall->rise for FPGA-centric;

-hold rise->rise,fall->fall for system-centric.

but all the constrain(multipath+false path) will introduce different desired setup/hold relationship.