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hrong4's avatar
hrong4
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7 years ago

hi someone has offered this question before,and is there any answer for it?

Hi. I have the difficulty to understand the different of set_multicyle_path in system approach and skew approach(FPGA centric) in AN433 doc. http://www.altera.com/literature/an/an433.pdf the cons...
sstrell's avatar
sstrell
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7 years ago

FPGA-centric means it's contained within the device itself. As such, the hold analysis happens at the same edge at the boundary of the FPGA as opposed to 1 cycle earlier which is where it would be for the "downstream" device. I would stick with the system-centric approach. It's easier to understand and implement. You can see a good explanation of AN433 in the associated online trainings:

https://www.intel.com/content/www/us/en/programmable/support/training/course/ocss1000.html

https://www.intel.com/content/www/us/en/programmable/support/training/course/oddr1000.html

#iwork4intel

  • hrong4's avatar
    hrong4
    Icon for New Contributor rankNew Contributor
    7 years ago

    sstrell,

    thanks for your response,but I still can not understand it.No matter fpga-centric or system-centric,the desired setup/hold relationship(data_clock and output_clock) should be the same.