Hi ALL... I need help with the HDL code

logic [4:0] clk_div_cnt = 1'd0;

logic clk_200KHz = 1'd0;

always @ (posedge clk_10MHz) begin : clk_divider_10MHz_to_200KHz

clk_div_cnt <= clk_div_cnt - 1'd1;

if (clk_div_cnt == 0) begin

clk_div_cnt <= 5'd24;

clk_200KHz <= ~clk_200KHz;

end

end

hi,

Can anyone tell me how to bringa 200Khz clock from 10Mhz clock??? I need to know how to write a verilog code for this? Please help with this

delay the enable one clock cycle.

Then you can detect if enable rised of falled by comparing it with the delayed version of it.

Hi,

ya that is the whole thing I have to do. So I splitted it up into two module. One with a faster clock and the other with SPI clock.

what I actually want to know is HI,

I have the following constraints. There is an enable. Whenever the enable goes low I have to take the incoming serial data at every posedge clk and I have to transfer the collected data as parallel out when the enable goes high. Now the serial data may be upto 75 bits. So I need to count the the number of clocks when enable is low and then transfer that many bits to out.

My question is how should I do this transfer. I have declared a register Count. I increment this by 1 every clock cycle when En=0; But how to guide the transfer to output.??? I want to transfer the collected bits to output when enable becomes 1 using the register count. And it should be transferred to out only once when the enable goes from low to high.

Please help me with this....

Thanks

ak

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Hi,

The enable waveform was given to me. When the enable goes low and in the pos edge of clock the data is taken in as long as the enable is low. I don't know whr from the signal comes.

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Hi,

what I mean is that you used in the if-statement "(SPI_EN == 0)", but in your code you never assign a value to "SPI_EN" and it is also not defined a input. I think it is a type error.

Let's talk about what your are trying to achieve.

Your inputs are SPI signals ( CLK, EN, DATA). According to the SPI spec ( as far as I know) the CLK is only active during the transmissing of the data. I assume you will do something with the data later on, so you have to transfer your data to a clock domain with a continuous running clock. What needs to be done ?

You have to generate a clk which runs much faster then the SPI clock. Re-sample all your inputs with a 3 bit shift register running with the fast clock. Now you can do all the processing the new clock domain. Look for risisng and falling edge of the SPI CLK and EN.

etc ...

Kind regards

GPK

Hi,

The enable waveform was given to me. When the enable goes low and in the pos edge of clock the data is taken in as long as the enable is low. I don't know whr from the signal comes.

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Hi

Im a beginner in HDL. I am given an SPI serial to parallel register and the inputs are clk, en and the serial data.. The register converts the serial data to parallel. The parallel data can be upto 50 bits... And also I need to detect the edge of the clock for re-sync. So I have to give the enable as input to a flipflop and and the ff output with the en to get edge detector o/p.

Please let me know whether my verilog code is correct.

module MY_MOD(

input DATA,

input EN,

input CLK,

output [49:0] OUT,

output EDGE_DETECT

);

reg [49:0] tmp;

reg [6:0] count;

reg tmp1;

//Read the serial data into a 75-bit register. Afterwards, convert it to parallel

always @(posedge CLK)

begin

tmp1 = EN;

if (SPI_EN == 0)

begin

count<=count+7'd1;

tmp = {tmp[48:0], DATA};

end

end

assign OUT = tmp;

assign EDGE_DETECT= EN & (!tmp1);

endmodule

Please suggest any change or corrections.

Thanks a load in advance

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Hi,

where is the signal SPI_EN coming from ?

Kind regards

GPK