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Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi ALL... I need help with the HDL code

Hi Im a beginner in HDL. I am given an SPI serial to parallel register and the inputs are clk, en and the serial data.. The register converts the serial data to parallel. The parallel data can be...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

logic [4:0] clk_div_cnt = 1'd0;

logic clk_200KHz = 1'd0;

always @ (posedge clk_10MHz) begin : clk_divider_10MHz_to_200KHz

clk_div_cnt <= clk_div_cnt - 1'd1;

if (clk_div_cnt == 0) begin

clk_div_cnt <= 5'd24;

clk_200KHz <= ~clk_200KHz;

end

end