Hi ALL... I need help with the HDL code

Hi,

ya that is the whole thing I have to do. So I splitted it up into two module. One with a faster clock and the other with SPI clock.

what I actually want to know is HI,

I have the following constraints. There is an enable. Whenever the enable goes low I have to take the incoming serial data at every posedge clk and I have to transfer the collected data as parallel out when the enable goes high. Now the serial data may be upto 75 bits. So I need to count the the number of clocks when enable is low and then transfer that many bits to out.

My question is how should I do this transfer. I have declared a register Count. I increment this by 1 every clock cycle when En=0; But how to guide the transfer to output.??? I want to transfer the collected bits to output when enable becomes 1 using the register count. And it should be transferred to out only once when the enable goes from low to high.

Please help me with this....

Thanks

ak