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Altera_Forum's avatar
Altera_Forum
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15 years ago

help with verilog syntax

Hi All,

lately i've encounter rather new verilog syntax for which i cannot find description or user guide.

i'm refereing to the exshastive use of colon with another operator

for example:

t1:=x(0) + x(8);

or

Data[j][SigDataCnt[j]*8+7-:8] <=TestCounter[7:0];

So if anyone can provide link to manual of this coding style i'd be thankful.

thnx.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The second expression is using indexed part-select which is explained in clause 4.2.1 vector bit-select and part-select addressing of the Verilog specification IEEE Std. 1364. The - sign is indicating a high to low vector index direction, the number after the colon the number of elements. Youd can use also +: for low to high indexes.

    := is a System Verilog syntax element describing distribuition weights, see IEEE Std. 1800-2005, clause 13.4 and 13.16.