Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Help with non-zero indexed signal vector/array

Not sure if this is the right posting site for general HDL queries, but here it goes: When declaring a scalar vector signal (e.g. bit_vector or std_logic_vector) or a multidimensional array in VHDL, I've seen both descending (downto) and ascending (to) syntax being used to constrain the range. Are there any restrictions on the upper or the lower bound of a signal/array? Is it perfectly legal to specify a signal that neither starts (for ascending) nor ends (for descending) with a zero index (i.e. zero-based numbering)?

E.g.

port (

a : in std_logic_vector (32 downto 24); -- msb of data bus

b : in std_logic_vector (5 to 7);

etc...

);

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Perfectly valid.As long as independent ports (i.e. a and b),it will concern only with range.

    (7 downto 0=15 downnto 8)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for clearing that up for me, but could you explain what you mean by "independent ports". For a specific example, if I have a set of chip select lines which is to be divided into memory segments (e.g. CS1~8 for bank1 data, CS9~16 for bank2 data, CS17~30 reserved for future use, CS31~CS40 bank1 checksum) but some of the lines in between are reserved and therefore no decoding logic shall be implemented. Which of the following is the preferred way (or the recommended way) of declaring output signals for ease of coding:

    1) Individual CS lines

    port (

    CS1, CS2, ... CS40 : out std_logic; -- omit CS17~30

    )

    2) Single std_logic_vector signal

    port (

    CS : out std_logic_vector (1 to 40); -- exclude CS17~30 from P&R pin assignment

    )

    3) Multiple std_logic_vector signals

    port (

    CS_B1 : out std_logic_vector (1 to 8);

    CS_B2 : out std_logic_vector (9 to 16);

    -- CS_RSV : out std_logic_vector (17 to 30);

    CS_B1_CHECKSUM : out std_logic_vector (31 to 41);

    )

    Thanks in advance.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    or even a 4th option, which is:

    port (

    CS_B1 : out std_logic_vector (0 to 7);

    CS_B2 : out std_logic_vector (0 to 7);

    -- CS_RSV : out std_logic_vector (0 to 13);

    CS_B1_CHECKSUM : out std_logic_vector (0 to 9);

    )