Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Help with non-zero indexed signal vector/array

Not sure if this is the right posting site for general HDL queries, but here it goes: When declaring a scalar vector signal (e.g. bit_vector or std_logic_vector) or a multidimensional array in VHDL, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

or even a 4th option, which is:

port (

CS_B1 : out std_logic_vector (0 to 7);

CS_B2 : out std_logic_vector (0 to 7);

-- CS_RSV : out std_logic_vector (0 to 13);

CS_B1_CHECKSUM : out std_logic_vector (0 to 9);

)