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Altera_Forum
Honored Contributor
Honored ContributorHelp with non-zero indexed signal vector/array
Not sure if this is the right posting site for general HDL queries, but here it goes: When declaring a scalar vector signal (e.g. bit_vector or std_logic_vector) or a multidimensional array in VHDL, ...
Altera_ForumHonored Contributor
Honored ContributorPerfectly valid.As long as independent ports (i.e. a and b),it will concern only with range.
(7 downto 0=15 downnto 8)
