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Altera_Forum
Honored Contributor
17 years agohelp urgently for a code
hi i like to translate this code verilog to code vhdl,
how i do this thank you
2 Replies
- Altera_Forum
Honored Contributor
Don't forget the QuartusII feature, when editing a VHDL file, you can do the menu pick edit -> insert template. If you plop down a whole design example, you can use that as a syntax framework. Or, if you are familiar with emacs as a text editor, it will keep you on the right track as well. After that, it's just "work"
- Altera_Forum
Honored Contributor
have a read in wikipedia - there should be enough there to help you out