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Altera_Forum
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16 years ago

help urgently for a code

hi i like to translate this code verilog to code vhdl, how i do this thank you
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Don't forget the QuartusII feature, when editing a VHDL file, you can do the menu pick edit -> insert template. If you plop down a whole design example, you can use that as a syntax framework. Or, if you are familiar with emacs as a text editor, it will keep you on the right track as well. After that, it's just "work"