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Altera_Forum's avatar
Altera_Forum
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14 years ago

help to get gate circuit

Hi, I want to get the gate circuit which shows in the handwrite gate circuit

so I wrote the VHDL code below 


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY memory_cell IS
PORT
	( I          :IN  std_logic;----input bit
	  W          :IN  std_logic;-----write_enable
	  S          :IN  std_logic;----select_enable
	  clk        :IN  std_logic;
	  q          :OUT std_logic------output bit
	  );
END memory_cell;
ARCHITECTURE structural OF memory_cell IS
SIGNAL J,K,J_g,K_g,Qa,Qb :std_logic;
ATTRIBUTE keep : boolean;
ATTRIBUTE keep OF J_g,K_g,Qa,Qb: SIGNAL IS true;
BEGIN
K <= NOT I AND W AND S;
J <= I AND W AND S;
K_g <= NOT (K AND clk AND Qa);
J_g <= NOT (J AND clk AND Qb);
Qa <= K_g NOR Qb;
Qb <= J_g NOR Qa;
q <= Qa;
END structural;

and I check the RTL Viewer, I get the image

but not the same, How do I change the code to get the same circuit?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi,

    There is one big problem with your implementation. Nobody can guaranty that a Flip-Flop or Latch build from discrete gates in a FPGA will work correctly. Then depending of the placement of the gates the routing can be very different especially for these crossing lines of the NOR gates.

    My advice to you is use the D-Flip-Flops in the FPGA to build the same functionality that your JK-Flip-Flop presents.

    The following code will implement your function: 

    
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY memory_cell IS
    PORT (
        I   : IN  std_logic;            ----input bit
        W   : IN  std_logic;            -----write_enable
        S   : IN  std_logic;            ----select_enable
        clk : IN  std_logic;
        q   : OUT std_logic             ------output bit
        );
END ENTITY memory_cell;
ARCHITECTURE structural OF memory_cell IS
    
    SIGNAL r : std_logic := '0';
    
BEGIN
    jk_ff: PROCESS (clk) IS
    BEGIN  -- PROCESS jk_ff
        IF rising_edge(clk) THEN        -- rising clock edge
            IF (W = '1' AND S = '1') THEN
                IF (I = '1') THEN       -- J = '1' -- set register
                    r <= '1';
                ELSE                    -- K = '1' -- reset register
                    r <= '0';
                END IF;
            END IF;
        END IF;
    END PROCESS jk_ff;
    q <= r;
    
END ARCHITECTURE structural;

    You don't even use the toggle functionality of a JK-Fliop-Flop so you could implement it with a RS-Flip-Flop instead if you still plan to build it with discrete gates.