Help me (Quartus 2)

:D Please!! Help me with this code. I do not know in reality that is incorrect. Thanks!

library ieee;

use ieee.std_logic_1164.all;

entity MUX_21 is

port(sel,gn: in std_logic;

A,B: in std_logic_vector(4 downto 1);

Y: out std_logic_vector(4 downto 1));

end MUX_21;

architecture sol of mux_21 is

signal f1,f2,f3,f4: std_logic;

begin

with sel select

f1<= a(1) when '0',

b(1) when others;

with sel select

f2<= a(2) when '0',

b(2) when others;

with sel select

f3<= a(3) when '0',

b(3) when others;

with sel select

f4<= a(4) when '0',

b(4) when others;

Y1<=f1 when gn='1' else '0';

Y2<=f2 when gn='1' else '0';

Y3<=f3 when gn='1' else '0';

Y4<=f4 when gn='1' else '0';

end sol;

Error (10482): VHDL error at MUX_21.vhd(30): object "Y1" is used but not declared