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Altera_Forum
Honored Contributor
Honored ContributorHelp me (Quartus 2)
:D Please!! Help me with this code. I do not know in reality that is incorrect. Thanks! library ieee; use ieee.std_logic_1164.all; entity MUX_21 is port(sel,gn: in std_logic; A,B: ...
Altera_ForumHonored Contributor
Honored ContributorWell the message says it... You declared a Y signal, but are trying to use Y1, that doesn't exist. I assume you meant Y(1)
