help for audio codec using VHDL

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hi

I'm trying to get the sound from adc and send the data to the dual port ram and i will control the system with nios but the most important part :when we get the data from WM8731; ı want to check the data like the leftdata and the right data . one port of ram will take the right data ,the other port of ram will take the leftdata .

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Usually, you use one port of RAM for input and the other for output. I am thinking you are making both ports read/write?

I would have one RAM for left channel data and another RAM for right channel data.

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ı run your adcdac controler code

and at first and second trying it is compiled. but now it is not .

ı hear the voice from only left side .

ın wm8731 datasheet some parameters (for ex. chipselect volume and etc but where did you define to use the left or right side ? how can use 2 part ?please help :S

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You can't "run" my "code". You mean that you are synthesizing my hardware description.

Anyway, I have reposted a student project in the link above. It also includes a detailed report on how the design works (check Report folder). In addition, the student project also includes simulating a set of nonlinear differential equations using Euler's method (note that this was originally Cornell University's Differential Analyzer, as cited in the project).

This should hopefully help you in understanding how to send data to and from the audio codec to a module (in this case neuronModel.vhd). You should configure the mega IP wizard FFT module and use it instead of the neuronModel.

Good luck.

Bart

hi

I'm trying to get the sound from adc and send the data to the dual port ram and i will control the system with nios but the most important part :when we get the data from WM8731; ı want to check the data like the leftdata and the right data . one port of ram will take the right data ,the other port of ram will take the leftdata .can you help me ? after that i will take fft so complicated . ı run your adcdac controler code

and at first and second trying it is compiled. but now it is not .

ı hear the voice from only left side .

ın wm8731 datasheet some parameters (for ex. chipselect volume and etc but where did you define to use the left or right side ? how can use 2 part ?please help :S

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First thank you for sharing this. It is clear and easy to read. But even with the most updated version I still have static when trying to playback the input signal. Do you not have this issue when running it? And if not why would my setup differ? I am using a DE1 with the 2C20F484C7 chip. Thank you

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The audio codec interface has been redesigned from scratch (modelSim simulation of the i2c controller, signalTap verification of the adc/dac data registers etc.):

http://myweb.msoe.edu/muthuswamy/digitalsystemsdesign/ee3921/audio/vhdl/de1audioadcdac.zip

Note that you should modify the design above to suit your requirements. Good luck.

Bart

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The code should be published at the Altera Wiki. It's much more instructive than the respective Terasic demonstration projects.

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Finally, I have the time this year to publish the stuff we develop. Anyway, altera wiki (http://www.alterawiki.com/wiki/de1_board)has been updated. direct link (http://myweb.msoe.edu/muthuswamy/digitalsystemsdesign/digitalsystemsdesign.html) to our digital systems website.

I will be making changes to the Altera Wiki and Digital Systems Website once/week (approximately Friday, around 5:00 pm CST) with new reference designs and bug fixes.

Thanks.

Bart

Thank you for your reply.

I decided to rewrite i2c_controller.v to i2c_controller.vhd by my own hands.

It works fine, just had to change name of some ports etc. :)

monmanmon, can u pls post/send me the i2c_controller that u have done? I really need it.

thank you..:)

I'll make you know.

Best regards

cb

Thank you for your reply.

I decided to rewrite i2c_controller.v to i2c_controller.vhd by my own hands.

It works fine, just had to change name of some ports etc. :)

Thank you for posting your code in tihis topic, it was very helpfull.

Best Regards,

Mon

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Hi,

I found this topic and it helped me alot. I spent a lot of hours in laboratory and have some problems with i2c.

What does it mean to "resythesize" verilog file? Does it mean to write it from scratch to vhdl file bo looking on verilog code? Or maybe there is some function in Quartus which does such thing (I can't find it in Quartus 9, I'm getting 10.1 now).

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No synthesis does not mean mapping verilog to VHDL. Synthesis means to obtain a "hardware design" from your verilog or VHDL specification. This hardware design can be of many forms: register-transfer level (RTL), state-machine or even at the "technology-map" level.

Ultimately, synthesis results in a file that can be placed and routed on your FPGA. For more information, read:

www.altera.com/literature/manual/intro_to_quartus2.pdf (http://www.altera.com/literature/manual/intro_to_quartus2.pdf)

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Maybe you could please post your project or implementation of i2c_controller for DE2? By looking on it I will try to figure out why my project doesn't work.

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The design for the DE1 and DE2 should be the same because both boards use the same audio codec. However, correctly map the pin assignments from my project for the DE1 to the DE2.

Good luck.

Bart