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Hi,
I found this topic and it helped me alot. I spent a lot of hours in laboratory and have some problems with i2c.
What does it mean to "resythesize" verilog file? Does it mean to write it from scratch to vhdl file bo looking on verilog code? Or maybe there is some function in Quartus which does such thing (I can't find it in Quartus 9, I'm getting 10.1 now).
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No synthesis does not mean mapping verilog to VHDL. Synthesis means to obtain a "hardware design" from your verilog or VHDL specification. This hardware design can be of many forms: register-transfer level (RTL), state-machine or even at the "technology-map" level.
Ultimately, synthesis results in a file that can be placed and routed on your FPGA. For more information, read:
www.altera.com/literature/manual/intro_to_
quartus2.pdf (
http://www.altera.com/literature/manual/intro_to_quartus2.pdf)
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Maybe you could please post your project or implementation of i2c_controller for DE2? By looking on it I will try to figure out why my project doesn't work.
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The design for the DE1 and DE2 should be the same because both boards use the same audio codec. However, correctly map the pin assignments from my project for the DE1 to the DE2.
Good luck.
Bart
Honored Contributor
