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Altera_Forum
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15 years agohelp for audio codec using VHDL
i am a begineer at using altera DE2 board and VHDL. i have to complete my project with in 10 days time but dont have any idea of where to start and how.. help .........
i need to build a duplex audio system that works similar to a phone but here CDMA must be considered. first i would like to have some good advice on where to start and how .... on audio CODEC any help would be more than appreciated72 Replies
- Altera_Forum
Honored Contributor
Hi,
I found this topic and it helped me alot. I spent a lot of hours in laboratory and have some problems with i2c. What does it mean to "resythesize" verilog file? Does it mean to write it from scratch to vhdl file bo looking on verilog code? Or maybe there is some function in Quartus which does such thing (I can't find it in Quartus 9, I'm getting 10.1 now). Maybe you could please post your project or implementation of i2c_controller for DE2? By looking on it I will try to figure out why my project doesn't work. Best regards, Mon - Altera_Forum
Honored Contributor
--- Quote Start --- first thank you for your replies. i tried both a ported version and the original verilog i2c controller (as your audio_codec_controller requests ans i2c_controller component). during lunch break i made a new project and i was not able to reproduce "varying static". but static is still present when sw1&9 are up (adc dac loopback), as moou pointed out, with or without input signal on line in - i've tried different i/o audio sources and the problem persists. initialization works fine as expected (5 on hex0) and sine/square wave generation works well too. maybe i'm missing some macroscopic point. anyways thank you for your help. best regards cb --- Quote End --- Hey cb, Two things I would recommend are: 1. Check the initialization commands to the registers for the audio codec. Make sure they are correct. 2. A very useful check would be to use SignalTap (or an external logic analyzer) and make sure the timing on the i2c bus lines and the left-channel/right-channel lines are correct. In my original design, I had a the dreaded "off by one clock cycle" bug. Again, I can only finish debugging the audio codec in a couple of weeks. In the meantime, do 1. and 2. above and repost if you find the bug. Bart - Altera_Forum
Honored Contributor
first thank you for your replies.
i tried both a ported version and the original verilog i2c controller (as your audio_codec_controller requests ans i2c_controller component). during lunch break i made a new project and i was not able to reproduce "varying static". but static is still present when sw1&9 are up (adc dac loopback), as moou pointed out, with or without input signal on line in - i've tried different i/o audio sources and the problem persists. initialization works fine as expected (5 on hex0) and sine/square wave generation works well too. maybe i'm missing some macroscopic point. anyways thank you for your help. best regards cb - Altera_Forum
Honored Contributor
Hey,
@carlo.bono: I believe my master FSM is designed to go through the initialization routine only once and get to a "stop" state. Hence you see a "5" (or "S" :D) on HEX0 where I output the current state of the master FSM. However the static is a more serious issue. But you say that you have a new i2c routine? However if your waveform generation works fine, why do you say the board adds static if no signal input is present? I am wondering if my interface to the data registers has issues with the new i2c routine. @ moou: Thanks for the vote of confidence, it will be another couple of weeks before I can get all the information up. I am designing a website that will incorporate all the course materials we have for digital systems at the Milwaukee School of Engineering (where I am an assistant prof.). This should include stuff on basic concepts, VGA, audio, NIOS, student projects etc. but all targeted for the DE1. I will post a link on the Altera wiki once this is done but it is taking me a while because of all the material I have to organize. But it should be done in a couple of weeks. Bart - Altera_Forum
Honored Contributor
It's the same with me too.
But again in brief. sw0 on & (sw8 sw9) off -> sine wave sw0 on & sw9 off & sw8 on -> square wave it is up to here is the same as in the comments:) sw0 on & sw9 on & sw8 off -> adc-dac-loopback + noise But mbharat will publish his code when he has once again revised. Stay tuned :) . - Altera_Forum
Honored Contributor
as someone pointed out, the code is very clear and I think really useful.
I've managed to use it with an i2c controller ported from altera's one, and the waveform generation just works fine. if i try loopback i have this result (with signal on line in): sw0+sw9 up: hex0 stuck on "5", static. every time i switch sw0 down and then up, static (volume varying between trials). basically, board now adds static to signal input, if present, or just plays static if no signal input is present. any hints? am I missing something? thank you in advance, best regards C - Altera_Forum
Honored Contributor
--- Quote Start --- thanks for the fast reply, I know that you dont posted a v. file, but I only have the i2c controller from the demonstrations of altera. I do not know where I can get an appropriate VHDL. To rewirte the existing .v to .vhd I understand not much enough verilog. --- Quote End --- Oh, I think I understand: your tried to port Terasic's audio codec verilog source to VHDL? To answer your question about appropriate VHDL, I had earlier posted in this thread my .VHDL audio codec interface. You can first just try to synthesize that and see if it works. Then you should go about reading the audio codec datasheet and try to understand the VHDL I posted. Mind you my i2c controller is not the best, I am working on an updated version. I will post that as soon as I am done. Second, as far as Terasic's audio codec verilog is concerned, I just resynthesized their HDL (from /DE1_CD_v0.8/DE1_i2sound/) on version 10.0 of Quartus. It synthesized fine, I didn't get any errors. Bart - Altera_Forum
Honored Contributor
thanks for the fast reply,
I know that you dont posted a v. file, but I only have the i2c controller from the demonstrations of altera. I do not know where I can get an appropriate VHDL. To rewirte the existing .v to .vhd I understand not much enough verilog. - Altera_Forum
Honored Contributor
--- Quote Start --- Hello, I have tried to replicate the project from mbharat. But I always get errors like: Error: Port "acknowledge" does not exist in macrofunction "i2cController" (same with done, i2c_scl, i2c_sda, readWriteEnable and start) Do I have the wrong I2C_Controller.v? Edit: I also have the DE1 board. --- Quote End --- I didn't post a .v file, my hardware is described using VHDL. Thanks. Bart - Altera_Forum
Honored Contributor
Hello,
I have tried to replicate the project from mbharat. But I always get errors like: Error: Port "acknowledge" does not exist in macrofunction "i2cController" (same with done, i2c_scl, i2c_sda, readWriteEnable and start) Do I have the wrong I2C_Controller.v? Edit: I also have the DE1 board.