Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi,
I found this topic and it helped me alot. I spent a lot of hours in laboratory and have some problems with i2c. What does it mean to "resythesize" verilog file? Does it mean to write it from scratch to vhdl file bo looking on verilog code? Or maybe there is some function in Quartus which does such thing (I can't find it in Quartus 9, I'm getting 10.1 now). Maybe you could please post your project or implementation of i2c_controller for DE2? By looking on it I will try to figure out why my project doesn't work. Best regards, Mon