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Altera_Forum
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15 years ago

help for audio codec using VHDL

i am a begineer at using altera DE2 board and VHDL. i have to complete my project with in 10 days time but dont have any idea of where to start and how.. help ......... i need to build a duplex au...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hey,

@carlo.bono: I believe my master FSM is designed to go through the initialization routine only once and get to a "stop" state. Hence you see a "5" (or "S" :D) on HEX0 where I output the current state of the master FSM. However the static is a more serious issue. But you say that you have a new i2c routine? However if your waveform generation works fine, why do you say the board adds static if no signal input is present? I am wondering if my interface to the data registers has issues with the new i2c routine.

@ moou: Thanks for the vote of confidence, it will be another couple of weeks before I can get all the information up. I am designing a website that will incorporate all the course materials we have for digital systems at the Milwaukee School of Engineering (where I am an assistant prof.). This should include stuff on basic concepts, VGA, audio, NIOS, student projects etc. but all targeted for the DE1.

I will post a link on the Altera wiki once this is done but it is taking me a while because of all the material I have to organize. But it should be done in a couple of weeks.

Bart