help for audio codec using VHDL

--- Quote Start ---

first thank you for your replies.

i tried both a ported version and the original verilog i2c controller (as your audio_codec_controller requests ans i2c_controller component).

during lunch break i made a new project and i was not able to reproduce "varying static". but static is still present when sw1&9 are up (adc dac loopback), as moou pointed out, with or without input signal on line in - i've tried different i/o audio sources and the problem persists.

initialization works fine as expected (5 on hex0) and sine/square wave generation works well too.

maybe i'm missing some macroscopic point. anyways thank you for your help.

best regards

cb

--- Quote End ---

Hey cb,

Two things I would recommend are:

1. Check the initialization commands to the registers for the audio codec. Make sure they are correct.

2. A very useful check would be to use SignalTap (or an external logic analyzer) and make sure the timing on the i2c bus lines and the left-channel/right-channel lines are correct. In my original design, I had a the dreaded "off by one clock cycle" bug.

Again, I can only finish debugging the audio codec in a couple of weeks. In the meantime, do 1. and 2. above and repost if you find the bug.

Bart

Hi,

I found this topic and it helped me alot. I spent a lot of hours in laboratory and have some problems with i2c.

What does it mean to "resythesize" verilog file? Does it mean to write it from scratch to vhdl file bo looking on verilog code? Or maybe there is some function in Quartus which does such thing (I can't find it in Quartus 9, I'm getting 10.1 now).

Maybe you could please post your project or implementation of i2c_controller for DE2? By looking on it I will try to figure out why my project doesn't work.

Best regards,

Mon

--- Quote Start ---

Hi,

I found this topic and it helped me alot. I spent a lot of hours in laboratory and have some problems with i2c.

What does it mean to "resythesize" verilog file? Does it mean to write it from scratch to vhdl file bo looking on verilog code? Or maybe there is some function in Quartus which does such thing (I can't find it in Quartus 9, I'm getting 10.1 now).

--- Quote End ---

No synthesis does not mean mapping verilog to VHDL. Synthesis means to obtain a "hardware design" from your verilog or VHDL specification. This hardware design can be of many forms: register-transfer level (RTL), state-machine or even at the "technology-map" level.

Ultimately, synthesis results in a file that can be placed and routed on your FPGA. For more information, read:

www.altera.com/literature/manual/intro_to_quartus2.pdf (http://www.altera.com/literature/manual/intro_to_quartus2.pdf)

--- Quote Start ---

Maybe you could please post your project or implementation of i2c_controller for DE2? By looking on it I will try to figure out why my project doesn't work.

--- Quote End ---

The design for the DE1 and DE2 should be the same because both boards use the same audio codec. However, correctly map the pin assignments from my project for the DE1 to the DE2.

Good luck.

Bart

Thank you for your reply.

I decided to rewrite i2c_controller.v to i2c_controller.vhd by my own hands.

It works fine, just had to change name of some ports etc. :)

Thank you for posting your code in tihis topic, it was very helpfull.

Best Regards,

Mon

I'll make you know.

Best regards

cb

Thank you for your reply.

I decided to rewrite i2c_controller.v to i2c_controller.vhd by my own hands.

It works fine, just had to change name of some ports etc. :)

monmanmon, can u pls post/send me the i2c_controller that u have done? I really need it.

thank you..:)

--- Quote Start ---

The code should be published at the Altera Wiki. It's much more instructive than the respective Terasic demonstration projects.

--- Quote End ---

Finally, I have the time this year to publish the stuff we develop. Anyway, altera wiki (http://www.alterawiki.com/wiki/de1_board)has been updated. direct link (http://myweb.msoe.edu/muthuswamy/digitalsystemsdesign/digitalsystemsdesign.html) to our digital systems website.

I will be making changes to the Altera Wiki and Digital Systems Website once/week (approximately Friday, around 5:00 pm CST) with new reference designs and bug fixes.

Thanks.

Bart

--- Quote Start ---

First thank you for sharing this. It is clear and easy to read. But even with the most updated version I still have static when trying to playback the input signal. Do you not have this issue when running it? And if not why would my setup differ? I am using a DE1 with the 2C20F484C7 chip. Thank you

--- Quote End ---

The audio codec interface has been redesigned from scratch (modelSim simulation of the i2c controller, signalTap verification of the adc/dac data registers etc.):

http://myweb.msoe.edu/muthuswamy/digitalsystemsdesign/ee3921/audio/vhdl/de1audioadcdac.zip

Note that you should modify the design above to suit your requirements. Good luck.

Bart