has mapped clock signal on user I/O

Hello Nivedisha,

i think i undestood ur problm,bt i need to have more details so can u pls give me more detailed description of what u have done with ur quartus project?

Have u created block diagram for ur system?

Becoz i feel it is a bit easy,just need to create two .bdf file in quartus 1) consists other components in ur system and 2) consists ur vhdl code

Then simple connect output from 1) to 2).means output clock from ur system (fpga) to input of ur vhdl.

this is right but i m afriad that i didnt understand ur question so better u give me more descrition of ur project.

Hope this will shed some light for ur question.

Hi Supal,

Thanks for your reply. But my question is slightly different than for what you have answered. I just need to know whether I can give a clock input on a user IO or not. As I have already given the clock on an IO in my board, can I use the clock using global routing for clock?

thanks

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Hello Nivedisha,

i think i undestood ur problm,bt i need to have more details so can u pls give me more detailed description of what u have done with ur quartus project?

Have u created block diagram for ur system?

Becoz i feel it is a bit easy,just need to create two .bdf file in quartus 1) consists other components in ur system and 2) consists ur vhdl code

Then simple connect output from 1) to 2).means output clock from ur system (fpga) to input of ur vhdl.

this is right but i m afriad that i didnt understand ur question so better u give me more descrition of ur project.

Hope this will shed some light for ur question.

--- Quote End ---

It would be nice to use proper English in stead of using 'texting short-cuts'?

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Hi Supal,

Thanks for your reply. But my question is slightly different than for what you have answered. I just need to know whether I can give a clock input on a user IO or not. As I have already given the clock on an IO in my board, can I use the clock using global routing for clock?

thanks

--- Quote End ---

Hi Nivedisha,

So from your reply,basically you wanted to know that "clock input" (fpga input) can be mapped on user IO or not,right?Because in first question,you said that you have mapped one of clocks on user IO which is OUTPUT clocks,and just now you said that you wonder if clock INPUT can be mapped or not.

Well,so if you are talking about the output clock mapping then it is upto you.You can mapped on anything as you have already done it.

If you are talking abt INPUT clock then I think it is not directly possible because as you already used it for IO mapping,

So if you want use that second clock for "IO mapping and vhdl application" then use PLL in your system,input of PLL= your second clock (that you wanted to mapped),generate two output clocks of same frequencies as input clock has and with NO DELAY.(In short input clock frequency=output clock1 frequency=output clock2 frequency)

Now you can use one of PLL output clocks as IO mapping and other is an input for your desired application.

Hope now it will help you little.