Altera_ForumHonored Contributor15 years agohas mapped clock signal on user I/O Hi, I am using arria II GX FPGA along with the ADC AD9268 on my board. I have two clock outputs from the FPGA which are used to latch the digitized output data from the ADC. I have mapped one o...Show More
Altera_ForumHonored Contributor15 years agoNivedisha,You can try connections for clocks as depicted in attached figure.clk.bmp328 KB
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