has mapped clock signal on user I/O

Hello Nivedisha,

i think i undestood ur problm,bt i need to have more details so can u pls give me more detailed description of what u have done with ur quartus project?

Have u created block diagram for ur system?

Becoz i feel it is a bit easy,just need to create two .bdf file in quartus 1) consists other components in ur system and 2) consists ur vhdl code

Then simple connect output from 1) to 2).means output clock from ur system (fpga) to input of ur vhdl.

this is right but i m afriad that i didnt understand ur question so better u give me more descrition of ur project.

Hope this will shed some light for ur question.