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Altera_Forum
Honored Contributor
Honored Contributorhas mapped clock signal on user I/O
Hi, I am using arria II GX FPGA along with the ADC AD9268 on my board. I have two clock outputs from the FPGA which are used to latch the digitized output data from the ADC. I have mapped one o...
Altera_ForumHonored Contributor
Honored ContributorYou can use any input pin as a clock in your design, but it won't be connected to the global clock network. This means that the timing will not be as good as with a real clock input, and you won't be able to use this clock as the input of a pll.
