Handling negation by synthesis tools

Hello!

Thank you for your response I looked into the .fit.rpt file, here is the snippet of it:

+------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+-------------------------------------------------------------+--------------------+-------+
; Resource ; Usage ; % ;
+-------------------------------------------------------------+--------------------+-------+
; Logic utilization (ALMs needed / total ALMs on device) ; 0 / 933,120 ; 0 % ;
; ALMs needed [=A-B+C] ; 0 ; ;
; [A] ALMs used in final placement [=a+b+c+d] ; 0 / 933,120 ; 0 % ;
; [a] ALMs used for LUT logic and register circuitry ; 0 ; ;
; [b] ALMs used for LUT logic ; 0 ; ;
; [c] ALMs used for register circuitry ; 0 ; ;
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 933,120 ; 0 % ;
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 933,120 ; 0 % ;
; [a] Due to location constrained logic ; 0 ; ;
; [b] Due to LAB-wide signal conflicts ; 0 ; ;
; [c] Due to LAB input limits ; 0 ; ;
; [d] Due to virtual I/Os ; 0 ; ;
; ; ; ;
; Difficulty packing design ; Low ; ;
; ; ; ;
; Total LABs: partially or completely used ; 0 / 93,312 ; 0 % ;
; -- Logic LABs ; 0 ; ;
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
; ; ; ;
; Combinational ALUT usage for logic ; 0 ; ;
; -- 8 input functions ; 0 ; ;
; -- 7 input functions ; 0 ; ;
; -- 6 input functions ; 0 ; ;
; -- 5 input functions ; 0 ; ;
; -- 4 input functions ; 0 ; ;
; -- <=3 input functions ; 0 ; ;
; Combinational ALUT usage for route-throughs ; 0

So, if I understand correctly, no logic resources (ALMs) were used to implement this negation?:

assign Q = ~ A;

Does that mean that I can use the negation of every bit in my project and it won't generate additional logic resources?

That's true, but only if we are talking about signals connected to LUTs, but what about, for example, signals connected to the output ports or to the register input ports? I belive there should be some additional logic to implement the negation in such cases?

Sure Here's a really small testcase (VQM file) that I've used:

module top(A, Q);
input A;
output Q;
assign Q = ~A;
endmodule

after implementation this generates 0 ALMs, as stated in my previous comments.

Hello!

sorry for the delayed reply. Yes, your comment about no logic resources (ALMs) used to implement the negation answers my question

Thanks for your help