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WaxyRakso's avatar
WaxyRakso
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3 years ago
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Handling negation by synthesis tools

Hi everyone, I have noticed, that sometimes synthesis tools (including Quartus) use direct negation in the VQM synthesis output file: assign Q = ~ A; or .dataa(!A), It seems that th...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    From what I get from Quartus is that there is no logic resources (ALMs) were used to implement the negation.

    You may test it out by using negation on every bit in your project or bigger design and see if it generate any additional logic resources.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Since there are no feedback for this thread and I believed I have answered your question.

With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.


  • WaxyRakso's avatar
    WaxyRakso
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello!

    sorry for the delayed reply. Yes, your comment about no logic resources (ALMs) used to implement the negation answers my question

    Thanks for your help