Forum Discussion
WaxyRakso
New Contributor
New ContributorHandling negation by synthesis tools
Hi everyone,
I have noticed, that sometimes synthesis tools (including Quartus) use direct negation in the VQM synthesis output file:
assign Q = ~ A;
or
.dataa(!A),
It seems that th...
From what I get from Quartus is that there is no logic resources (ALMs) were used to implement the negation.
You may test it out by using negation on every bit in your project or bigger design and see if it generate any additional logic resources.
VenT_Altera
Frequent Contributor
Frequent ContributorHi,
Do you mind to send us a small design to do further investigation?
Thanks.
WaxyRaksoSure
Here's a really small testcase (VQM file) that I've used: module top(A, Q);
input A;
output Q;
assign Q = ~A;
endmoduleafter implementation this generates 0 ALMs, as stated in my previous comments.
