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WaxyRakso's avatar
WaxyRakso
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3 years ago
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Handling negation by synthesis tools

Hi everyone, I have noticed, that sometimes synthesis tools (including Quartus) use direct negation in the VQM synthesis output file: assign Q = ~ A; or .dataa(!A), It seems that th...
  • RichardT_altera's avatar
    3 years ago

    From what I get from Quartus is that there is no logic resources (ALMs) were used to implement the negation.

    You may test it out by using negation on every bit in your project or bigger design and see if it generate any additional logic resources.