Forum Discussion
New ContributorHandling negation by synthesis tools
From what I get from Quartus is that there is no logic resources (ALMs) were used to implement the negation.
You may test it out by using negation on every bit in your project or bigger design and see if it generate any additional logic resources.
Super ContributorYou can look through the Fitter Resources Usage summary to see which type of resources is used.
You may also open and look through the .fit.rpt for further details.
For my case, the fitter used the I/O pins and I can see the message below indicate that as well.
Info (169124): Fitter converted 5 user pins into dedicated programming pins
WaxyRaksoHello!
Thank you for your responseI looked into the .fit.rpt file, here is the snippet of it:
+------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+-------------------------------------------------------------+--------------------+-------+
; Resource ; Usage ; % ;
+-------------------------------------------------------------+--------------------+-------+
; Logic utilization (ALMs needed / total ALMs on device) ; 0 / 933,120 ; 0 % ;
; ALMs needed [=A-B+C] ; 0 ; ;
; [A] ALMs used in final placement [=a+b+c+d] ; 0 / 933,120 ; 0 % ;
; [a] ALMs used for LUT logic and register circuitry ; 0 ; ;
; [b] ALMs used for LUT logic ; 0 ; ;
; [c] ALMs used for register circuitry ; 0 ; ;
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 933,120 ; 0 % ;
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 933,120 ; 0 % ;
; [a] Due to location constrained logic ; 0 ; ;
; [b] Due to LAB-wide signal conflicts ; 0 ; ;
; [c] Due to LAB input limits ; 0 ; ;
; [d] Due to virtual I/Os ; 0 ; ;
; ; ; ;
; Difficulty packing design ; Low ; ;
; ; ; ;
; Total LABs: partially or completely used ; 0 / 93,312 ; 0 % ;
; -- Logic LABs ; 0 ; ;
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
; ; ; ;
; Combinational ALUT usage for logic ; 0 ; ;
; -- 8 input functions ; 0 ; ;
; -- 7 input functions ; 0 ; ;
; -- 6 input functions ; 0 ; ;
; -- 5 input functions ; 0 ; ;
; -- 4 input functions ; 0 ; ;
; -- <=3 input functions ; 0 ; ;
; Combinational ALUT usage for route-throughs ; 0
So, if I understand correctly, no logic resources (ALMs) were used to implement this negation?:assign Q = ~ A;Does that mean that I can use the negation of every bit in my project and it won't generate additional logic resources?
