Forum Discussion
New ContributorHandling negation by synthesis tools
From what I get from Quartus is that there is no logic resources (ALMs) were used to implement the negation.
You may test it out by using negation on every bit in your project or bigger design and see if it generate any additional logic resources.
Regular ContributorLogic functions in FPGAs are implemented via lookup tables that are programmed to implement the desired logic function.
So negation of any signal, input or output, basically comes for free. Just change the contents of the lookup table.
Invert bits as necessary to reflect output signal negation, or shuffle the order of entries to reflect input signal negation.
New ContributorThat's true, but only if we are talking about signals connected to LUTs, but what about, for example, signals connected to the output ports or to the register input ports? I belive there should be some additional logic to implement the negation in such cases?
