GXB tx_coreclk source problem

Hi!

Quartus prime 16.1.1 Build 200 11/30/2016 Sj Standard Edition

PartNumber EP4SGX530NF45C2

I have the following problem:

I'm trying to configure a PCIe serdes (alt_gxb) and I need to drive transmit clock from PLL (not from serdes output clock).

According to the Stratix IV handbook (Volume 2, table 2-16), I need to set "GXB 0 PPM core clock" setting from PLL output to serdes data output:

 set_instance_assignment -name GXB_0PPM_CORE_CLOCK ON -from "pll_125:pll_125_inst|altpll:altpll_component|clk" -to serdes_TX_P

But it does not help.

I keep receiving the error:

Error (167028): Input port CORECLK of GXB Transmitter channel PCS "serdes_1x:DUT|serdes_1x_alt4gxb:serdes_1x_alt4gxb_component|transmit_pcs0" must be fed by output port CLOCK_OUT of GXB Transmitter channel PCS "serdes_1x:DUT|serdes_1x_alt4gxb:serdes_1x_alt4gxb_component|transmit_pcs0" because the GXB transmitters have the same clock rate or are operating in bonded x4/x8 mode

If I drive transmit clock from another GXB and have this setting "GXB_0PPM_CORE_CLOCK" configured - that causes no error in compilation.

But I need to drive it from PLL.

The handbook claims I can drive

"Clock output from left and right and top and bottom PLLs (PLL_L, PLL_R, and PLL_T, PLL_B)"

The partnumber has a few PLLs, named (PLL_B1/2, PLL_T1/2, PLL_L1/2/3/4, PLL_R1/2/3/4) but making a location assignment does not affect the error.

Any advice?

p.s. attached a project template with the error