Forum Discussion
4 Replies
- Ash_R_Intel
Regular Contributor
Hi,
Please let us know which FPGA device you are targeting to.
You may refer to documents available:
- AN-731: Simultaneous Switching Noise Guidelines for Intel Cyclone 10 LP, Cyclone IV, and Cyclone III Devices
- Device design guidelines
- AN 75: High-Speed Board Designs
- Pin connection guidelines
Regards.
- Karunakaran
New Contributor
Targeting to Max 10 10M08SAU169I7G
- ak6dn
Regular Contributor
How are you measuring that 400mV noise on your ground? What is the test lead setup into the oscilloscope input?
A less than optimal probing setup can induce false noise into your measurement.
You must be probing 'ground' with respect to 'ground', correct? But where are these two points located?
- Ash_R_Intel
Regular Contributor
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