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Altera_Forum's avatar
Altera_Forum
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12 years ago

Good way to generate /WE signal?

Hi all!

Does anyone have any suggestions for generating a (negative-logic) write-enable signal for an async ram? The ram I'm (planning) to use has a 0ns data/address hold time and since I'd like to keep everything single-clock, my current 'solution' is to OR-in a logic-high with the clock signal so when I clock that low, the last half of the clock would be my write-enable, as in:

assign we_n = clk | memwrite;

where memwrite is clocked synchronously and would normally be high.Glitches *should* be minimal and not long enough to prevent unwanted writes.

Alternatively, I could divide my clock by 2 or 4 and then make it all synchronous, which would allow me to create a nice half-clock period on either side of the write-enable but that kinda limits my performance which I'd like to keep at at least 50mhz.

Any ideas?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Usually keeping everything as synchronous as possible will make life easier in the long run and easier to debug.

    And where is this mythical memory with a 0ns hold time from?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Yeah, I know keeping things synchronous is better but like I said earlier, it'd reduce my overall performance at the cost of (potentially) increased noise due to the higher frequency and it's only for this one signal. With regards to the hold time, I meant data and address hold time at the end of write ( tHD, tHA). Most of ISSI's memories list this as 0ns (S64WV6416DBLL/DBLS for instance, page 14). Unless I'm on crack, of course..:)

    Either way, what's your preferred way to generate a write signal? Half the frequency and clock it on falling edges or divide by 4 and use positive edges?

    -Mux
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    0 ns hold time is typical for many async RAMs. But you'll need to add a margin for FPGA timing skew, or strictly constrain the IO timing.

    I remember that I have used a dedicated PLL-generated RAM write clock with specific phase shift and duty cycle in a design to utilize async RAM to the maximum.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Yeah, that's kinda why I asked. I've done writes in the past using CMOS components (breadboarded!) which worked because the propagation delay was long enough to not make a difference. Doubt I'll use a PLL but it's an interesting option, thanks for that!