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Altera_Forum's avatar
Altera_Forum
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12 years ago

Good way to generate /WE signal?

Hi all! Does anyone have any suggestions for generating a (negative-logic) write-enable signal for an async ram? The ram I'm (planning) to use has a 0ns data/address hold time and since I'd lik...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Yeah, I know keeping things synchronous is better but like I said earlier, it'd reduce my overall performance at the cost of (potentially) increased noise due to the higher frequency and it's only for this one signal. With regards to the hold time, I meant data and address hold time at the end of write ( tHD, tHA). Most of ISSI's memories list this as 0ns (S64WV6416DBLL/DBLS for instance, page 14). Unless I'm on crack, of course..:)

Either way, what's your preferred way to generate a write signal? Half the frequency and clock it on falling edges or divide by 4 and use positive edges?

-Mux