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Altera_Forum
Honored Contributor
Honored ContributorGood way to generate /WE signal?
Hi all! Does anyone have any suggestions for generating a (negative-logic) write-enable signal for an async ram? The ram I'm (planning) to use has a 0ns data/address hold time and since I'd lik...
Altera_ForumHonored Contributor
Honored ContributorYeah, that's kinda why I asked. I've done writes in the past using CMOS components (breadboarded!) which worked because the propagation delay was long enough to not make a difference. Doubt I'll use a PLL but it's an interesting option, thanks for that!
