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Altera_Forum
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13 years ago

Good way to generate /WE signal?

Hi all! Does anyone have any suggestions for generating a (negative-logic) write-enable signal for an async ram? The ram I'm (planning) to use has a 0ns data/address hold time and since I'd lik...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

0 ns hold time is typical for many async RAMs. But you'll need to add a margin for FPGA timing skew, or strictly constrain the IO timing.

I remember that I have used a dedicated PLL-generated RAM write clock with specific phase shift and duty cycle in a design to utilize async RAM to the maximum.