glitich in the outputs

I mean put a D flip flop on your output.

Glitching output -> DFF -> Glitch free output

Use the same clock that you are using for your state machine. The only draw back is that the output will be delayed by 1 clock cycle.

thank you for the reply, you mean i should use a register for the output, i have 2 process the first one is for current state process( synchronous process) which is clocked process to detrmine the current state while the second process is for Next State and output Logic Process (combinational process) that does not have clcok ,

so what u mean , you want to make registered process for the output

, so clock should be used as it is registred

or what you mean exactely

Are you driving the output from a combinatorial block? When the inputs to a combinatorial block change, the data propagates through the block and can cause glitches on the output prior to settling.

You can either inforce state mapping on your input to prevent this or put a register on the output.

Creating state mappings and custom logic to prevent glitches doesn't always work because Quartus tends to optimize them out. Registering the output always works but you have to have a clock in your design and the output will be one clock cycle late.