Honored Contributori am getting some glitiched in the outputs, i am not sure what is the reason of then glitich and how to get rid of them, the glitichs happen in the output that are not changing
Honored ContributorHere is the attached file
Honored ContributorTHANK YOU FOR THE REPLY,, according to the codes you have seen already, as i am downloading these codes to the FPGA , and the changes of LEDs need to be slow to be recognized by human vision, and the board has 50Mhz CLOCK, how to add some codes to the existing codes to divide the clcok rather than using manual bushbutton as clcok, so i can use the internal clock of the FPGA,,
thank you so muchHonored Contributoryou dont want to slow the clock, you want to generate clock enables so that things only change when the enable is active. Dividing the clock (without a PLL, which wont work at low frequencies) will cause setup and hold violations.
Honored Contributorclcok enable, how this is done on my VHDL codes, where to do it on my codes,,so i can try it on the FPGA
Honored ContributorI JUST would like to let you that two things have happened with the new codes
1- the output is delayed by one clcok tick 2-the rest has no effect in the system so how can i make my output changes immedately after the rising clock and make my rest effects and resets the machine to idle stateHonored Contributorall actions happen in the next rising edge
Honored Contributoris there any way i could make changes accour in the rising edge instaed of being delayed one edge
Honored ContributorThey do change on the rising edge. The delay comes from the fact the outputs are registered. If you wanted no delay, you'd have to have combinatorial outputs, which was glitching previous.
It should not cause any problems.Honored Contributori really do not like this delay on my program as i am applying these codes to the FPGA chip and i want everything on order,
is there any way to get rid from those glitiches without causing a delay to the outputs, is there anychanges could be made to this process to amke the changes in the outputs happen without delayHonored ContributorNo - you'll have to get used to this "delay" - its called pipelining.
It is not really a delay - the only problem will be uderstanding the wave form.
