i am getting some glitiched in the outputs, i am not sure what is the reason of then glitich and how to get rid of them, the glitichs happen in the output that are not changing

Are you driving the output from a combinatorial block? When the inputs to a combinatorial block change, the data propagates through the block and can cause glitches on the output prior to settling. You can either inforce state mapping on your input to prevent this or put a register on the output. Creating state mappings and custom logic to prevent glitches doesn't always work because Quartus tends to optimize them out. Registering the output always works but you have to have a clock in your design and the output will be one clock cycle late.

thank you for the reply, you mean i should use a register for the output, i have 2 process the first one is for current state process( synchronous process) which is clocked process to detrmine the current state while the second process is for Next State and output Logic Process (combinational process) that does not have clcok , so what u mean , you want to make registered process for the output , so clock should be used as it is registred or what you mean exactely

I mean put a D flip flop on your output. Glitching output -> DFF -> Glitch free output Use the same clock that you are using for your state machine. The only draw back is that the output will be delayed by 1 clock cycle.

Standard Mealy or Moore FSM designs, e.g. the Quartus HDL templates don't register the output signals, resulting in glitches. You should register those signals, that are fed to output pins. Another option to design the FSM in a single clocked process. All signals will be registered without specific means.

i already added the clock to the senstivity list in the process that performs the outputs but i still have the glitches

glitich in the outputs | Altera Community

33 Replies

Altera_Forum
Honored Contributor
14 years ago
so even if we make 3 processes this will not solve the problem of glitiches,, do you think this glitches will effect the performance of the designed circuit
Altera_Forum
Honored Contributor
14 years ago
the 3rd process I suggested would have the same effect of the single process state machine I posted.

I really cant tell you if the glitches will cause issues. It really depends on the timing parameters of the connected device.
Altera_Forum
Honored Contributor
14 years ago
thank you for the reply, it is now clear ,, i am still looking for the clock enable and how to put it in my program i mean in which part to slow the internal frequncy of the board,

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glitich in the outputs

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