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Altera_Forum's avatar
Altera_Forum
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17 years ago

glitch curiosity

Hallo friends,

At simulation stage, Quartus reports some combinational glitches found, all of them under 1nS. Few questions:

1) How accurate is this in real world?

2) The curious part is some glitches appears when I remove some "Outputs" from design, defined only for simulation process.

So can we conclude that outputs (wires) exists in real world and acts as capacitive loads, making small delays on gate paths? Or just simulator thinks that way, glitches disappears in sim but they still remain in real world?

Thanks very much for clarifying this problem,

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I think, that removal of outputs mainly results in a modified place and route of the design, which already causes timing differences. In my opinion, the simulator can't predict exactly the existence or absence of combinational glitches for a particular output. If you send unregistered combinational signals to outputs, glitches must be expected as the general case.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Are you saying that your simulated "outputs" would not really be outputs in your real design? If they are just nets that will normally be connected to other parts of the design then I'd say you can ignore them. The simulator is just letting you know that there are glitches on the outputs of the design you are simulating.

    Signals "glitch" all over the place inside the FPGA. This is just the normal transient behavior with combinatorial logic. Whether it's classified as normal or problematic behavior depends on what the signal is driving.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Yes, I have many "outputs" not connected to any out pins, just defined in schematic for timing analysis purpose.

    However, I noticed adding few "outputs" in parallel, will actually modify those glitches (even elsewhere than additionally loading) so I also guess simulator just take into account loading, translating in further delay on wires.

    My app is async, and suppose to drive (internally) some counters (reset, latch, etc) simplifying old glued logic, so glitches are bad here :(

    Resuming, if they appears in sim can I rely they are also in real program and vice versa, glitches free in sim means for sure free in CPLD?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I would certainly not rely on the simulator to tell me if I'm glitch-free. Better instead to use design techniques that guarantee glitch-free operation. Registering all the outputs is the best way to do this. If you've got a state machine and it seems too difficult to change the machine to register all the outputs, you could change the state machine to use output-encoding.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    I would certainly not rely on the simulator to tell me if I'm glitch-free. Better instead to use design techniques that guarantee glitch-free operation.

    --- Quote End ---

    Indeed! I have to get use to synch world :) After some combinational logic I have, I inserted a dff, clocked by main clock (which is sufficiently greater than this part of design, so 1 tck delay isn't important) and this signal becomes glitch-free.

    After this, all my signals become nice & clean. Tnx for advices!