glitch curiosity

Are you saying that your simulated "outputs" would not really be outputs in your real design? If they are just nets that will normally be connected to other parts of the design then I'd say you can ignore them. The simulator is just letting you know that there are glitches on the outputs of the design you are simulating.

Signals "glitch" all over the place inside the FPGA. This is just the normal transient behavior with combinatorial logic. Whether it's classified as normal or problematic behavior depends on what the signal is driving.

Jake