Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorglitch curiosity
Hallo friends, At simulation stage, Quartus reports some combinational glitches found, all of them under 1nS. Few questions: 1) How accurate is this in real world? 2) The curious part...
Altera_ForumHonored Contributor
Honored ContributorI think, that removal of outputs mainly results in a modified place and route of the design, which already causes timing differences. In my opinion, the simulator can't predict exactly the existence or absence of combinational glitches for a particular output. If you send unregistered combinational signals to outputs, glitches must be expected as the general case.
