Honored Contributor
Honored ContributorYes, I have many "outputs" not connected to any out pins, just defined in schematic for timing analysis purpose.
However, I noticed adding few "outputs" in parallel, will actually modify those glitches (even elsewhere than additionally loading) so I also guess simulator just take into account loading, translating in further delay on wires. My app is async, and suppose to drive (internally) some counters (reset, latch, etc) simplifying old glued logic, so glitches are bad here :( Resuming, if they appears in sim can I rely they are also in real program and vice versa, glitches free in sim means for sure free in CPLD?
