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Altera_Forum's avatar
Altera_Forum
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13 years ago

Getting the System Time in VHDL

Hello,

Attached below is my VHDL code for a digital clock. Right now the code sets the default time as 12:00:00 AM, as seen from lines 35-38. I was wondering if there was some sort of command in VHDL to get the current time from the computer, just for the first time you run the program onto the board (although if I could do it with a button press, that would be great as well). Or if there is some other way to do so. It looks like I will have to use Nios II, just making sure that I don't have to.

Also any advice about the code in general is always welcome.

Thanks in advance,

Marcin

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    There isn't anything like that.

    The default time will be hardcoded into the design during compilation.

    At best, you could have a way to automatically set the time of the compilation as the default time for your clock.

    There isn't any VHDL command for this, AFAIK, but you can use a generic and TCL script to set the generic's value.

    But short of you adding a network interface, with a UDP/IP stack and a NTP client implementation or something of the sort, there's no way for your design to automatically retrieve the computer's time.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    hello,

    i want to know digital alarm clock using VHDL(clock need to show on LCD)

    for DE2 board.

    if you know, plz share me :)

    thx