I notice that derive_pll_clocks produces a souce name in my design of -source [get_pins {q_sys_inst|enet_pll|sd1|pll7|inclk[0]}].However the node name "q_sys_inst|enet_pll|sd1|pll7|inclk[0]" doesnt get listed in any of the netlist viewers.How am I supposed to use create_generated clocks on things which arent PLLs if I cant easily view the node name to be able to use get_pins?

I think if you use the Keep attribute within the source code then you can use the Verilog/VHDL netnames in the sdc file. Seems to work anyhow.

get_pins | Altera Community

sstrell
Super Contributor
2 years ago
derive_ commands make it easy to create SDC for internal nodes of IP that you don't ever need to reference. For your own logic, just use the Name Finder accessed from any of the GUI dialog boxes you can use from the text editor to add SDC. And you don't have to use derive_pll_clocks if you don't want to (though you should). The -source could just as easily be the input clock pin to the PLL, easily found with the Name Finder..
ShengN_altera
Super Contributor
2 years ago
Hi,

Do you have any further concern or consideration on this thread?

Thanks,
Best Regards,
Sheng
- NGord
  Occasional Contributor
  2 years ago
  derive only works for PLLs
  Name finder doesnt obviously indicate the source fro a clock which is generated out of a mux or logic.
  Any other suggestions such as using the keep attribute in the RTL?
  - sstrell
    Super Contributor
    2 years ago
    That's what the clocks report is for. Identify what pins/ports the tool thinks are clocks and create clock constraints for them. If it's a clock that you are generating yourself, then you should know what the source should be and include it in the create_generated_clock command.
    For a simple example, if you create a divide-by-two clock with a register and a feedback inverter, the clock target is the Q output of the register and the source is the D input.