Forum Discussion
NGord
Occasional Contributor
Occasional Contributorget_pins
I notice that derive_pll_clocks produces a souce name in my design of -source [get_pins {q_sys_inst|enet_pll|sd1|pll7|inclk[0]}]. However the node name "q_sys_inst|enet_pll|sd1|pll7|inclk[0]" ...
I think if you use the Keep attribute within the source code then you can use the Verilog/VHDL netnames in the sdc file. Seems to work anyhow.
sstrell
Super Contributor
Super ContributorThat's what the clocks report is for. Identify what pins/ports the tool thinks are clocks and create clock constraints for them. If it's a clock that you are generating yourself, then you should know what the source should be and include it in the create_generated_clock command.
For a simple example, if you create a divide-by-two clock with a register and a feedback inverter, the clock target is the Q output of the register and the source is the D input.
NGordOccasional Contributor
Occasional ContributorI think if you use the Keep attribute within the source code then you can use the Verilog/VHDL netnames in the sdc file. Seems to work anyhow.
